Embodiments of the present invention relate to a high speed, low power dynamic amplifier circuit for analog circuit applications.
Analog-to-digital conversion is used in a wide variety of electronic devices to convert analog signals to digital domain signals. This conversion facilitates signal processing for a variety of applications such as digital communications, medical imaging, digital video, xDSL cable modems, and fast Ethernet. There are a variety of analog-to-digital converter (ADC) circuits for various applications. For example, successive approximation register (SAR) circuits or oversampling sigma-delta ADCs may be desirable for low sampling rates. Flash ADCs may be desirable for higher sampling rates. Pipelined ADC circuits, however, have become the most popular architecture for sampling rates of a few megasamples per second (Msps) to more than 100 Msps. Moreover, pipelined ADCs may include plural stages of Flash ADCs.
FIG. 1 is a typical 12-bit pipelined ADC circuit of the prior art. The ADC circuit includes four 3-bit stages 100-106 and a time alignment and error correction circuit 108. Stages 2-4 (102-106) are similar to stage 1 (100) as shown in detail. Stage 1 is coupled to receive analog input signal Vin. Sample-and-hold circuit 110 samples Vin at a predetermined clock frequency and applies the samples to 3-bit ADC circuit 112 and to sum circuit 116. ADC circuit 112 produces the three most significant bits (MSBs) of the 12-bit digital word and applies them to circuit 108. The three MSBs are also applied to 3-bit digital-to-analog (DAC) circuit 114. DAC 114 applies an analog version of the three MSBs to sum circuit 116. The analog version of the three MSBs is subtracted from the held analog version of Vin to produce a residue signal. The residue signal is then amplified by four (×4) by residue amplifier 118 and applied to stage 2 (102). The process continues in subsequent stages until all 12 bits of the digital words are resolved. An important advantage of the pipelined ADC is that stage 1 can receive and process new samples of input signal Vin as soon as the residue signal is received by the sample-and-hold circuit of stage 2.
FIG. 2 is an exemplary 3-bit ADC circuit 112 of the prior art. The circuit includes eight resistors connected in series between voltage sources V+ and V− to produce respective reference voltages VR6 through VR0. Each reference voltage is applied to one input terminal of a respective comparator, such as comparators 202-204. A second input terminal of each comparator is coupled to receive input signal Vin. A corresponding 3-bit digital output signal is shown on the right. For example, if Vin is greater than reference voltage VR6, the 3-bit digital output is 111. If Vin is greater than reference voltage VR5 and less than VR6, the 3-bit digital output is 110. A problem occurs, however, when the input voltage is near a reference voltage. For example, when Vin is slightly more than VR3 and less than VR4, a small difference voltage V3 is applied to the input terminals of comparator 202. By way of comparison, a greater difference voltage V4 is applied to comparator 200. Likewise, a greater difference voltage V2 is also applied to comparator 204. In a similar manner, all other comparators receive a greater difference voltage than comparator 202. The problem is that comparator 202 may remain in a metastable state due to the small difference voltage while other comparators switch to their final states. Thus, comparator 202 is subjected to noise from other comparators of the array while its final state remains undetermined. Thus, comparator 202 may produce one or more bit errors in the pipeline ADC.
Referring to FIG. 3, there is a simplified circuit diagram of a comparator circuit of the prior art that may be used in the comparator array of FIG. 2. The comparator circuit includes an amplifier circuit formed by NPN transistors 300 and 302, n-channel transistor 304, and load resistors RL. The comparator circuit also includes a latch circuit formed by NPN transistors 306 and 308, n-channel transistor 310, and output resistors RO as indicated. A current source 312 is coupled to the common source terminal of n-channel transistors 304 and 310. In operation, when clock signal CLK is low and complementary clock signal /CLK is high, n-channel transistor 304 is on and the amplifier circuit is enabled. N-channel transistor 310 is off, and the latch circuit is disabled. Plus input signal Vip is applied to the base of NPN transistor 300, and minus input signal Vim is applied to the base of NPN transistor 302. Input transistors 300 and 302 produce corresponding output signals Vom and Vop. When complementary clock signal /CLK goes low and clock signal CLK goes high, the amplifier circuit is disabled by n-channel transistor 304 and the latch circuit is enabled by n-channel transistor 310. NPN transistors 306 and 310 latch the state of output signals Vom and Vop received from the amplifier circuit. If output signals from the amplifier circuit are in a metastable or undetermined state, however, they may be latched in an incorrect state or even remain in an undetermined state. The comparator gain may be increased and the corresponding amplifier time constant decreased by increasing the current through current source 312. This has the disadvantage of increasing power consumption as well as array noise. The period of clock signal CLK may also be increased, thereby providing more time for the amplifier circuit to amplify the difference voltage between Vip and Vim. Of course, this has the disadvantage of reducing speed of the ADC.
While preceding approaches may provide improvements in ADC speed and throughput, the present invention is directed to further improvements in speed, throughput, and an improved error rate. Accordingly, the preferred embodiments described below are directed toward improving upon the prior art.